With the realization of high-speed and high-integration semiconductor devices, metal lines formed within semiconductor devices are becoming finer, and being formed with multi layers. In such a case, however, the widths of the metal lines get reduced as well, so that a signal delay occurs due to resistance and capacitance of the metal lines. Thus, to reduce such a signal delay, copper having a low resistance has been widely employed for the formation of metal lines.
In comparison with conventional metals employed, copper is difficult to etch. Accordingly, a copper wiring is formed through a damascene process including the steps of: forming a trench ; then forming a copper layer to fill the trench; and finally performing a chemical mechanical polishing process thereon.
Since, however, copper tends to diffuse into another layer easily, a diffusion barrier film is formed on the trench before filling the trench with copper.
Though the diffusion barrier film can be formed of Ta, a Ta film cannot prevent a diffusion of copper perfectly. For this reason, the diffusion barrier film has been formed of TaN. However, the TaN film has a defect in that its adhesive strength with copper is low, though it can prevent diffusion of copper more effectively than a Ta film.
Currently, the diffusion barrier film is formed of a dual film of Ta/TaN to improve the reliability of the semiconductor device. The dual-film diffusion barrier film can be formed by using a physical vapor deposition (PVD), an atomic layer deposition (ALD) or a chemical vapor deposition (CVD). In comparison to the CVD method or ALD method, the PVD method is simple and also a thin film formed thereby has a higher purity.
However, when the dual-film barrier layer is formed by the PVD method, there may occur an overhanging phenomenon in which an entrance of a via is blocked, if an aspect ratio of the via is great, which results in a failure to form a barrier layer appropriately.